1. Field of the Invention
The present invention particularly relates to a semiconductor device having a CMOS driver circuit.
2. Description of the Background Art
In recent years, semiconductor devices each including a plurality of processing circuits have been produced as one-chip microcomputers and these semiconductor devices have been utilized for electronic circuit equipment or the like of, for example, cellular phones. While a portable equipment such as a cellular phone necessarily employs a battery as a power supply, the battery is made small in size and light in weight to satisfy the demand to do so.
Since it is demanded to employ the battery for long time besides such a demand for making the battery small in size and light in weight, it is strongly demanded to decrease the power consumption of the battery. On the other hand, for a digital cellular phone or the like, it is further demanded to accelerate the semiconductor device so as to digitally process a voice signal at real time.
In order to meet these various demands, normally, a signal processing section in a circuit is constituted out of transistors each of which has a low current driving force to propagate processed signals to an internal circuit and a circuit, which outputs signals to the outside, employs a driver circuit consisting of transistors each having a high current driving force.
FIG. 31 is a circuit block diagram of a conventional CMOS driver circuit which propagates an input signal. In the following description, the CMOS driver circuit will be also referred to as simply “driver circuit”.
Referring to FIG. 31, the conventional CMOS driver circuit includes two inverters INV0 and INV1 which are connected in series. Inverter INV0 includes transistors PT0 and NT0. Transistor PT0 is arranged between a power supply voltage VDD and a node Na and the gate thereof is connected to an input node to receive the input of an input signal IN. Transistor NT0 is arranged between node Na and a ground voltage GND and the gate thereof receives the input of input signal IN.
Inverter INV1 includes transistors PT1 and NT1. Transistor PT1 is arranged between power supply voltage VDD and an output node and the gate thereof is connected to node Na. Transistor NT1 is arranged between the output node and ground voltage GND and the gate thereof is connected to node Na. It is noted that transistors PT0 and PT1 are P-channel MOS transistors and transistors NT0 and NT1 are N-channel MOS transistors.
Further, inverter INV1 outputs a signal transmitted to the output node as an output signal OUT.
In the following description, the input node from which input signal IN is received is also denoted by reference symbol IN and the output node from which output signal OUT is driven is also denoted by reference symbol OUT.
Referring to a timing chart shown in FIG. 32, the operation of the conventional CMOS driver circuit will be described. In the following, it is assumed that power supply voltage VDD is 1 V and ground voltage GND is 0 V by way of one example. In addition, it is assumed that high voltage level (power supply voltage VDD: 1 V) is “H” level and low voltage level (ground voltage GND: 0 V) is “L” level.
In an initial state, it is assumed that input signal IN is 0 V. In this case, transistor PT0 of inverter INV0 is turned on to thereby electrically couple power supply voltage VDD to node Na. Therefore, the voltage level of node Na is set at 1 V. In addition, transistor NT1 of inverter INV1 is turned on in response to the voltage level of node Na to thereby electrically couple ground voltage GND to the output node. Therefore, the voltage level of the output node is set at 0 V.
If input signal IN changes from 0 V to 1 V at time T1, transistor PT0 is turned off and transistor NT0 is turned on in inverter INV0. In response to this, ground voltage GND is electrically coupled to node Na and the voltage level of node Na is set at 0 V. In inverter INV1, transistor PT1 is turned on in response to the voltage level of node Na to thereby electrically couple power supply voltage VDD to the output node. Therefore, the voltage level of the output node is set at 1 V. Output signal OUT rises at time T1a after the elapse of the transistor operation delay time since time T1 and set at 1 V.
If input signal IN changes from 1 V to 0 V at time T2, transistor NT0 of inverter INV0 is turned off and transistor PT0 thereof is turned on. In response to this, power supply voltage VDD is electrically coupled to node Na and the voltage level of node Na is set at 1 V. In addition, in response to the voltage level of node Na, transistor PT1 of inverter INV1 is turned off and transistor NT1 thereof is turned on. As a result, the output node is electrically coupled to ground voltage GND and the voltage level of the output node is set at 0 V.
As described above, in the CMOS driver circuit, output signal OUT is propagated as the level of input signal IN changes from “L” level to “H” level or from “H” level to “L” level.
The output node is normally electrically connected to a circuit in the next stage and a parasitic capacitance, a resistance or the like caused by the input capacitance and wirings of the circuit in the next stage becomes output load. In order to propagate output signal OUT at high rate in response to input signal IN, it is necessary to accelerate the operation rates of transistors PT1 and NT1 which constitute inverter INV1 in an output stage. Specifically, the channel widths of transistors PT1 and NT1 which constitute inverter INV1 in an output stage are set larger than those of transistors PT0 and NT0 which constitute inverter INV0 in the first stage to thereby accelerate signal propagation rate. If the gate length of each transistor is, for example, 0.1 μm, the gate widths of transistors PT0, NT0, PT1 and NT1 are set at approximately 2 μm, 1 μm, 10 μm and 5 μm, respectively.
As described above, the conventional CMOS driver circuit is normally constituted to accelerate signal propagation rate by setting the gate width of the inverter in the output stage which constitutes the driver circuit large.
However, as transistor microfabrication technique advances, a gate oxide film becomes thinner and a so-called gate leak current which is carried from a gate to a source or a drain or a substrate disadvantageously increases.
FIG. 33 shows the relationship between the thickness of a gate oxide film and gate leak current per transistor. Namely, FIG. 33 is a leak current characteristic view of a transistor which is set to have a gate length of 0.1 μm and a gate width of 10 μm.
In FIG. 33, the horizontal axis indicates the thickness of the gate oxide film and the vertical axis indicates the gate leak current (unit A: ampere) per transistor.
The gate leak current shown herein means a current which leaks from a gate terminal to a source, a drain and a substrate terminal if power supply voltage VDD is connected to the gate terminal and ground voltage GND is connected to each of the source, the drain and the substrate terminal for the N-channel MOS transistor. For the P-channel MOS transistor, the gate leak current means a current which leaks from a source, a drain and a substrate terminal to a gate terminal if ground voltage GND is connected to a gate terminal and power supply voltage VDD is connected to each of the source, the drain and the substrate terminal.
In a generation in which a transistor has a gate length of approximately 0.18 μm, the thickness of the gate oxide film of the transistor is approximately 260 nm. Gate leak current will now be considered in a case where the gate width is set at 1 μm.
The gate leak current shown in FIG. 33 is almost proportional to a gate area. For example, if the thickness of the gate oxide film is approximately 260 nm, the gate length is 0.1 μm and the gate width is 10 μm, the gate leak current of the transistor is about 1E−14 (A). It is assumed that 1E−14 indicates —14th power of 1×10. This applies hereafter. In this case, if the gate length is 0.18 μm and gate width is 1 μm, a gate leak current per transistor is about 1.8E−15 (A).
On the other hand, a sub-threshold leak current which is carried between the source and the drain if the transistor is in a standby state is about 1E−12 (A) under the same setting conditions as those described above. Therefore, the sub-threshold leak current is far higher than the gate leak current and it is unnecessary to consider the quantity of the gate leak current in the generation in which the transistor has a gate length of approximately 0.18 μm.
Recently, however, as the microfabrication technique has developed and demand for acceleration of operation rate has been rising, the thickness of a gate oxide film decreases and the gate leak current cannot be ignored. For example, in the generation of a gate length of 0.1 μm, the gate oxide film is set to have a thickness of approximately 200 nm.
Referring to FIG. 33, if the gate width is 10 μm, the gate leak current of the transistor is calculated as approximately 1E−11 (A). If the transistor is designed to have a gate length of 0.1 μm and a gate width of 1 μm, the gate leak current is calculated as approximately 1E−12 (A). Therefore, the leak current which is almost equal to the sub-threshold leak current flows and cannot be ignored. In this way, as the gate leak current of a transistor increases following the development of the microfabrication technique, the power consumption of the entire circuit disadvantageously increases.
Further, as already described above, the gate leak current is proportional to the gate area of a transistor. As a result, the gate leak current increases particularly in a transistor employed in the final stage of a driver current and having a larger gate width.
In order to decrease such a leak current, Japanese Patent Laying-Open No. 2001-156260 discloses a method for stopping power supply and thereby suppressing a leak current if a circuit, in which transistors having different gate oxide film thicknesses are provided, the gate oxide film of each transistor is small and the gate leak current is high, is inoperative. However, according to this method, it is necessary to provide a constitution for controlling the supply of power in accordance with the operative state and the inoperative state of the circuit. Further, wait time for changing an operative mode to an inoperative mode is required, which obstructs high rate operation.